A practical approach to DSP code optimization using compiler/architecture

Authors

  • B. Varnagirytė Aalborg University
  • A. Žemelis Aalborg University
  • O. Olsen Aalborg University
  • P. Koch Aalborg University
  • O. Wolf DSP Assist
  • E. Kazanavičius Kaunas University of Technology

Keywords:

DSP compiler efficiency, C-code optimization, instruction level parallelism, compiler-architecture interaction, FIR filter, LMS algorithm, profiling

Abstract

This paper addresses DSP compiler efficiency issues. It examines C-code optimization and coding techniques for computationally intensive algorithm implementation on a DSP architecture in order to anticipate the efficiency of the compiler-generated code. The key result was, that for small experiments the built-in optimizations combined with manual compensation for known shortcomings of the compiler accounted for the major part of achievable improvements in cycle count and code size. Also, the compiler proved insensitive to various language constructs with equal semantics.

Unfortunately the same results were not reproducible for a larger algorithm.

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Published

2002-08-28

Issue

Vol. 43 No. 2 (2002)

Section

SIGNAL PROCESSING

License

Copyright terms are indicated in the Republic of Lithuania Law on Copyright and Related Rights; Articles 4-37.
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